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Simulate computation from the gate level up, in code. Implement the basic gates (AND/OR/NOT/XOR) — ideally building the others from NAND to prove its universality — compose them into a half-adder then a ripple-carry FULL ADDER for n-bit addition, and then build a tiny von-Neumann CPU: registers, a memory array, a program counter, and a FETCH–DECODE–EXECUTE loop over a small instruction set (e.g. LOAD, ADD, STORE, JMP, HALT). Run a sample program (such as summing an array) and trace the register/PC state each cycle. No hardware — pure simulation.
Gates correct (bonus: built from NAND); the n-bit full adder produces correct sums and carry — verified against known cases.
A working fetch-decode-execute loop over registers + memory + PC; the instruction set executes a non-trivial sample program correctly.
The model reflects real architecture (program and data in memory; instructions are data; a clocked cycle), not a hand-waved shortcut.
Per-cycle state is observable/traceable; tests or a worked run demonstrate correctness.
Use this README structure to make the work reviewable.
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# A logic-gate & CPU simulator ## Goal Simulate computation from the gate level up, in code. Implement the basic gates (AND/OR/NOT/XOR) — ideally building the others from NAND to prove its universality — compose them into a half-adder then a ripple-carry FULL ADDER for n-bit addition, and then build a tiny von-Neumann CPU: registers, a memory array, a program counter, and a FETCH–DECODE–EXECUTE loop over a small instruction set (e.g. LOAD, ADD, STORE, JMP, HALT). Run a sample program (such as summing an array) and trace the register/PC state each cycle. No hardware — pure simulation. ## Acceptance criteria - [ ] Gates & adder: Gates correct (bonus: built from NAND); the n-bit full adder produces correct sums and carry — verified against known cases. - [ ] CPU model: A working fetch-decode-execute loop over registers + memory + PC; the instruction set executes a non-trivial sample program correctly. - [ ] Faithfulness: The model reflects real architecture (program and data in memory; instructions are data; a clocked cycle), not a hand-waved shortcut. - [ ] Trace & tests: Per-cycle state is observable/traceable; tests or a worked run demonstrate correctness. ## Verification - [ ] Document installation and run commands. - [ ] Record automated checks and their exact commands. - [ ] Add representative output, screenshots, or a short demo where useful. - [ ] Confirm failure paths and known constraints. ## Decision log ### Decision title - Context: - Choice: - Alternatives considered: - Tradeoffs: ## Evidence - Link each rubric criterion to the file, test, or artifact that demonstrates it. ## Known limitations - List what is intentionally out of scope and what should be improved next.